The present invention relates to a line driver for data transmission, in particular a line driver for wirebound data transmission at high bit rates.
A conventional line driver known from the prior art for wirebound data transmission is represented by way of example in FIG. 4.
As is shown in FIG. 4, the line driver comprises several parallel-connected differential pairs 3, with in each case two transistors 4, 5, wired in accordance with FIG. 4, in the present case NMOS field effect transistors, of which the source connections are connected to a power source 25, which supplies an impressed current I01 . . . IOn. The drain connections of the two transistors 4, 5, which are also designated hereinafter as differential pair transistors, of each differential pair are connected to the source connections of further transistors 6 and 7 respectively, which in each case are driven by their gate connections with a bias voltage of a voltage source 8 and 9 respectively. The transistors 6 and 7 provided jointly for all differential pairs 3 form with the differential pair transistors 4 and 5 respectively in each case a cascade circuit, and are consequently also referred to hereinafter as cascade transistors. The drain connections of the cascade transistors 6, 7, are connected to the load outputs of the line driver, as is indicated in FIG. 4 in the form of (external) load resistors 12 and 13.
The differential pairs 3 are variously deflected or actuated as a function of the data of the line driver which is to be transmitted, i.e. as a function of the output signal which is to be transmitted, and drive a current onto the common cascade transistors 6, 7. The deflection or actuation of each differential pair 3 is effected by connecting the gate connections of the differential pair transistors 4, 5, to two different reference voltages Vref1 and Vref2 as a function of a digital word imposed, i.e. to be transmitted. To this purpose, the differential pair transistors 4, 5, are imposed by means of controllable switches 26–29, as a function of complementary control signals DW or DW respectively, optionally to the reference voltage Vref1 and Vref2 in such a way that the differential pair transistors 4, 5, are actuated in a differentially symmetrical manner, i.e. the gate connection of the differential pair transistor 4 is located, for example, at the reference voltage Vref1, while at the same time the gate connection of the differential pair transistor 5 is imposed at the reference voltage Vref1 and vice-versa. The reference voltages Vref1 and Vref2 are, as shown in FIG. 4, generated via a series circuit arrangement of a power source 26, which supplies an impressed current Iref, with two further transistors 27 and 28, which are connected as represented in FIG. 4. The voltage differential |Vref1−Vref2| determines the actuation level swing of the individual differential pairs 3.
As can be seen from FIG. 4, in the example represented all the transistors are designed in the form of NMOS field effect transistors.
One problem with the circuit arrangement shown in FIG. 4 lies in the fact that the differential pair transistors 4, 5, are actuated with a different edge gradient. The time constant Tr (for a rising edge) or Tf respectively (for a falling edge) of the individual actuation signal can in a first approximation be calculated as follows:
                                          T            r                    =                                    C              G                        ·                          (                                                1                                      g                    mref1                                                  +                                  1                                      g                    mref2                                                              )                                      ⁢                                  ⁢                              T            f                    =                                    C              G                        ·                          1                              g                mref2                                                                        (        1        )            
In this situation, CG represents the gate capacitance of the differential pair transistors 4, 5, and gmrof1 or gmrof2 represent the gradient of the differential pair transistors 4, 5, as a function of the reference voltage Vref1 or Vref2 respectively. As a result of the different time constants for a rising edge and a falling edge of the actuation signal, the differential pair transistors 4, 5, are deflected at different speeds. Accordingly, unsymmetrical edges occur at the load outputs of the line driver, as well as an AC voltage or AC signal at the foot point of the individual differential pair 3 in each case, as a result of which instances of non-linearity are incurred. This DC voltage couples via the parasitical capacitances of the current mirror circuit or cascade transistors 6, 7 onto the bias voltage provided by the voltage sources 8, 9, and therefore changes briefly the voltage provided, whereby this effect is dependent on the number of simultaneously switched differential pairs 3, and is therefore also dependent on the particular output signal of the line driver which is being sent.
The cascade transistors 6, 7, reduce the signal level swing at the drain connections of the differential pair transistors 4, 5, which as a rule are very large, and determines the load impedance for the situation in which the impedance value RL of the resistors 12, 13, is less than 1/gos, i.e. less than the reciprocal output guideline value of the cascade transistors 6, 7, this load impedance being seen from the individual differential pair 3 in each case, or which takes effect on the individual differential pair 3.
As a function of the output signal which is to be sent, a signal current of differing level flows through the cascade transistors 6, 7. Because the output guideline value gDS of the cascade transistors 6, 7, depends on the current IDS through the cascade transistors, a signal-dependent load takes effect on the differential pair transistors 4, 5, which leads to non-linearities.
In addition to this, when the reference voltages Vref1 and Vref2 are switched over, voltage peaks or spikes occur, which can likewise have a negative effect on the linearity of the line driver. Moreover, the reference voltages Vref1 and Vref2 created in accordance with FIG. 4 by means of diode voltages of the transistors 27, 28, fluctuate perceptibly as a function of the ambient temperature and the manufacturing process, which has a negative effect on the stability of the circuit arrangement.
The present invention is therefore based on the object of providing a line driver with improved linearity. In addition to this, the line driver should also satisfy the usual requirements such as, for example, low supply voltage and low power consumption and area coverage.
According to the invention, the line driver comprises several driver stages connected in parallel, which in each case comprise a differential pair with two transistors which are actuated in a differential manner as a function of the data which is to be transmitted. In addition to this, a separate cascade transistor pair is allocated to each differential pair, i.e. by contrast with the prior art represented in FIG. 4, the individual differential pair transistors are not connected to a common cascade transistor pair, but in each case to a separate cascade transistor pair. The individual driver stages are connected via the individual cascade transistor pairs in parallel to the load outputs of the line driver.
The summation of the currents of the individual driver stages is effected in the signal path “behind” the individual cascade transistors. Because in the deflected or actuated state, there is always a maximum current flowing through the one cascade transistor of each driver stage, and always a minimum current flowing through the other cascade transistor of the individual driver stage in each case, the load impedance of the differential pair of the individual driver stage, seen in differential consideration, is independent of the signal amplitude. This property increases the linearity of the line driver.
A further improvement in linearity can be achieved in that the differential pair transistors are actuated with the aid of a suitable preliminary stage or control circuit, in such a way that an actuation of the minimum current through one branch or transistor of the differential pair is not zero, but that a low quiescent current is flowing. It is true that an adequate linearity will be guaranteed if the minimum current through a branch is zero, but nevertheless the linearity is better with a quiescent current which differs from zero. The preliminary stage of the individual driver stage is designed in such a way that it can be adjusted relatively precisely to the common mode level and to the signal level swing, independently of each other. Because the preliminary stage allows for an independent adjustment and setting of the common mode level and of the signal level swing of the control signals for the actuation of the individual differential pair transistors in each case, an adjustable and symmetrical edge gradient of the transmission signal can be achieved; i.e. the same time constants are guaranteed for rising edges and for falling edges of the control signals, which serve to actuate the differential pair transistors in each case.
In the preliminary stages or control circuits, which in each case are provided for the actuation of the differential pair transistors of a corresponding driver stage, transfer gates are used instead of the NMOS transistors conventionally used, in order for the linearity of the switch for the deflection of the individual lift current to be increased, in order thereby to increase the symmetry of the signal edges used for the actuation of the individual differential pair transistors, and to suppress the occurrence of an AC signal at the foot point of the individual differential pair. By means of this measure too, the linearity of the transmission signal will also be increased.
Overall, therefore, it is possible with the aid of the present invention for a line driver to be created which, in addition to the usual requirements, such as low supply voltage, for example, or low power consumption and surface area, also has a high linearity and a high, adjustable, and symmetrical edge gradient of the transmission signals. In this situation, the present invention is particularly well-suited for the realisation of high-linear line drivers for a wirebound data transmission with high bit rates, for use, for example, in fast Ethernet transmission or transmission/reception devices. Naturally, however, the present invention is not restricted to this preferred scope of application, but can be applied in every situation in which high-linear transmission signals are desirable, i.e. in particular with a wireless data transmission.
The present invention is described in greater detail hereinafter by reference to the appended drawings, on the basis of a preferred embodiment.